Journals
Publish with us
Publishing partnerships
About us
Blog
VLSI Design
Table of Contents
Special Issues
VLSI Design
/
2014
/
Article
/
Fig 2
/
Research Article
High-Efficient Circuits for Ternary Addition
Figure 2
The proposed ternary half adder (#Tube = 3), (a) Sum generator subcircuit, (b) Carry generator subcircuit.
(a)
(b)