High-Efficient Circuits for Ternary Addition

Table 5

Simulation results of one-digit adders.

Design	V			V			V
	Delay; (psec)	Power; (μW)	PDP; (aJ)	Delay; (psec)	Power; (μW)	PDP; (aJ)	Delay; (psec)	Power; (μW)	PDP; (aJ)
	Ternary half adder
Proposed; THA	38.74	0.282	10.94	28.42	0.880	25.01	25.43	2.778	70.66
THA by; Lin et al. [16]	91.40	0.771	70.43	66.64	2.291	152.7	54.03	5.817	314.3
THA by; Moaiyeri et al. [17]	50.35	0.415	20.88	39.49	1.264	49.91	35.08	3.806	133.5
	Ternary full adder
Proposed; TFA	58.94	0.456	26.89	43.95	1.472	64.68	35.66	4.595	163.9
TFA by; Ebrahimi et al. [18]	189.5	0.597	113.1	139.4	1.893	263.9	116.8	5.463	638.3
TFA by; Keshavarzian and Sarikhani [19]	119.2	0.607	72.32	102.4	1.912	195.9	81.98	5.413	443.8