High-Efficient Circuits for Ternary Addition

Table 8

Simulation results of 7-TIT ternary ripple adders.

Design	Delay; (psec)	Power; (μW)	PDP; (fJ)	#Transistors	Total width; (nm)
Ripple adder by; the proposed THA and TFA	187.84	7.5778	1.4234	916	54960
Ripple adder by; THA-112T and THF-132T	371.84	9.9079	3.6841	904	54240