High-Efficient Circuits for Ternary Addition

Table 9

Bulk CMOS model parameters.

Parameter	Description	Value
	Physical channel length	32 nm
	The effective gate channel length	12.6 nm
	The source and drain resistance per unit channel width	150 Ω-μm
	The gate oxide thickness	1 nm
	The gate-to-bulk overlap capacitance per unit channel length	25.6 pF/m
/	The overlap capacitance between gate and lightly doped drain/source region	265.3 pF/m