Research Article
Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic
Table 2
Probability of abnormal power and output error rate over all possible input patterns for DCVSL logic gates.
| | DCVSL gates | Percentage of abnormal power over all input patterns | Percentage of output error over all input patterns |
| | Inverter | 50.00% | 100% | | XOR2 | 41.66% | 100% | | XOR3 | 33.92% | 100% | | AND2 | 25.00% | 25.00% | | AND3 | 12.50% | 12.50% | | OR2 | 25.00% | 50.00% | | OR3 | 12.50% | 25.00% | | OAI21 | 23.21% | 28.57% | | AOI21 | 26.78% | 50.00% | | AOI22 | 25.89% | 45.08% | | OA22 | 25.89% | 35.27% | | MUX21 | 30.35% | 55.00% |
| | Average | 27.72% | 52.00% |
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