Radix-2^α/4^β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

Table 1

Resources needed to compute an FFT of size 𝑁.

Butterfly structure	Complex multiplier	Complex adder	Latency (cycles)	𝑇 (Spc)
4 parallel BPE architectures
R-2^4 [13], [14]	4(log4𝑁−1)	16log4𝑁	𝑁/4	4
R-2^4 [15]	4(log4𝑁−1)	16log4𝑁	𝑁/4	4
R-2^4 [16]	4(log4𝑁−1)	16log4𝑁	𝑁/4	4
R-2^2 [17]	3(log4𝑁−1)	16log4𝑁	𝑁/4	4
R-2^3 [17]	4(log4𝑁−1)	8log4𝑁	𝑁/4	4
R-2^4 [17]	3.5(log4𝑁−4)	8log4𝑁	𝑁/4	4
Proposed MuxMDC-R2^2	3(log4𝑁−1)	4log4𝑁	𝑁/4	4
8 parallel BPE architectures
R-2 [18]	8(log4𝑁−1)	16log4𝑁	𝑁/8	8
R-2 [19]	8(log4𝑁−1)	32log4𝑁	𝑁/8	8
R-2^4 [20]	8(log4𝑁−1)	32log4𝑁	𝑁/8	8
R-2^2 [17]	6(log4𝑁−1)	16log4𝑁	𝑁/8	8
R-2^3 [17]	6log4𝑁−7	16log4𝑁	𝑁/8	8
R-2^4 [17]	7log4𝑁−8	16log4𝑁	𝑁/8	8
Proposed MuxMDC-R2^3	7(log8𝑁−1)	8log8𝑁	𝑁/8	8
16 parallel BPE architectures
Proposed MuxMDC-R2^4	17(log16𝑁−1)	16log16𝑁	𝑁/16	16
Proposed MuxMDC-R4^2	15(log16𝑁−1)	32log16𝑁	𝑁/16	16