Radix-2^α/4^β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

Table 2

Resources needed in terms of FA to compute an FFT of size 𝑁.

Butterfly structure	FA
4 parallel BPE architectures
R-2^4 [13], [14]	12𝑛^2log4𝑁−1+20𝑝log4𝑁−1+32𝑝log4𝑁
R-2^4 [15]	12𝑛^2log4𝑁−1+20𝑝log4𝑁−1+32𝑝log4𝑁
R-2^4 [16]	12𝑛^2log4(𝑁−1)+20𝑝log4(𝑁−1)+32𝑝log4𝑁
R-2^2 [17]	9𝑛^2log4𝑁−1+15𝑝log4𝑁−1+32𝑝log4𝑁
R-2^3 [17]	12𝑛^2(log4𝑁−1)+20𝑝log4𝑁−1+16𝑝log4𝑁
R-2^4 [17]	10.5𝑛^2log4𝑁−1+17.5𝑝log4𝑁−1+16𝑝log4𝑁
Proposed MuxMDC-R2^2	9𝑛^2log4𝑁−1+15𝑝log4𝑁−1+8𝑝log4𝑁
8 parallel BPE architectures
R-2 [18]	24𝑛^2log4𝑁−1+40𝑝log4𝑁−1+32𝑝log4𝑁
R-2 [19]	24𝑛^2log4𝑁−1+40𝑝log4𝑁−1+64𝑝log4𝑁
R-2^4 [20]	24𝑛^2log4𝑁−1+40𝑝log4𝑁−1+64𝑝log4𝑁
R-2^2 [17]	18𝑛^2log4𝑁−1+30𝑝log4𝑁−1+32𝑝log4𝑁
R-2^3 [17]	18𝑛^2log4𝑁−1+30𝑝log4𝑁−1+32𝑝log4𝑁−21𝑛^2−35𝑝
R-2^4 [17]	21𝑛^2log4𝑁−1+35𝑝log4𝑁−1+32𝑝log4𝑁−24𝑛^2−40𝑝
Proposed MuxMDC-R2^3	21𝑛^2log8𝑁−1+35𝑝log8𝑁−1+16𝑝log8𝑁
16 parallel BPE architectures
Proposed MuxMDC-R2^4	51𝑛^2log16𝑁−1+85𝑝log16𝑁−1+32𝑝log16𝑁
Proposed MuxMDC-R4^2	45𝑛^2log16𝑁−1+75𝑝log16𝑁−1+64𝑝log16𝑁