On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

<table>Absolute power consumption for 64-bit, 32-bit, and 16-bit bus, with encoding (E), serialization-widening (SW), and serialization-widening with encoding (SWE) normalized to 64-bit bus width for 32 KB L1 cache.</table>

VLSI Design

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Figure 12

Figure 12: On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding 