On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

<table>Comparison of the % of power savings using the different data bus power reduction approaches. Results are compared to a conventional 64-bit L1-L2 cache data bus at 45 nm technology.</table>

VLSI Design

fig6

Figure 6

Figure 6: On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding 