On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

Table 2

Comparison of possible approaches to reduce on-chip data bus power.

	Approach	Bus freq.	Switching activity	Line cap.	Bus area
1	C (conventional)	f	𝛼C	𝐶C	Original bus area
2	S (serial)	2f	𝛼S	𝐶S	Reduced
3	W (widened)	f	𝛼C	𝐶W	At least double
4	E (encoded)	f	𝛼E	𝐶C	Unchanged
5	SW	2f	𝛼S	𝐶SW	Unchanged
6	SE	2f	𝛼SE	𝐶S	Reduced
7	WE	f	𝛼E	𝐶W	At least double
8	SWE	2f	𝛼SE	𝐶SW	Unchanged