Journals
Publish with us
Publishing partnerships
About us
Blog
VLSI Design
Table of Contents
Special Issues
VLSI Design
/
2014
/
Article
/
Tab 3
/
Research Article
Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity
Table 3
Resource requirements of proposed architecture using folding method.
Parameter
Multipliers
Adders
Minimum clock period (ns)
Total delay (ns)
Speed
(MHz)
Total dynamic power (mW)
Value
58
518
16.033
256.528
3.898
1019