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VLSI Design
Volume 2014 (2014), Article ID 872501, 10 pages
Review Article

VLSI Architectures for Image Interpolation: A Survey

1Department of ECE, St. Xavier’s Catholic College of Engineering, Nagercoil 629003, India
2Department of ECE, Mepco Schlenk Engineering College, Sivakasi 626005, India

Received 18 October 2013; Revised 20 April 2014; Accepted 5 May 2014; Published 19 May 2014

Academic Editor: Marcelo Lubaszewski

Copyright © 2014 C. John Moses et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Image interpolation is a method of estimating the values at unknown points using the known data points. This procedure is used in expanding and contrasting digital images. In this survey, different types of interpolation algorithm and their hardware architecture have been analyzed and compared. They are bilinear, winscale, bi-cubic, linear convolution, extended linear, piecewise linear, adaptive bilinear, first order polynomial, and edge enhanced interpolation architectures. The algorithms are implemented for different types of field programmable gate array (FPGA) and/or by different types of complementary metal oxide semiconductor (CMOS) technologies like TSMC 0.18 and TSMC 0.13. These interpolation algorithms are compared based on different types of optimization such as gate count, frequency, power, and memory buffer. The goal of this work is to analyze the different very large scale integration (VLSI) parameters like area, speed, and power of various implementations for image interpolation. From the survey followed by analysis, it is observed that the performance of hardware architecture of image interpolation can be improved by minimising number of line buffer memory and removing superfluous arithmetic elements on generating weighting coefficient.