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VLSI Design
Volume 2015, Article ID 256474, 9 pages
http://dx.doi.org/10.1155/2015/256474
Research Article

Functional Testbench Qualification by Mutation Analysis

1Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
2Institute of Very Large Scale Integrated Circuit Design, Zhejiang University, Hangzhou 310027, China
3Laboratory of Computer Science, Institute of Software, Chinese Academy of Sciences, Beijing 100080, China

Received 2 February 2015; Revised 16 April 2015; Accepted 26 April 2015

Academic Editor: Avi Ziv

Copyright © 2015 Kai Huang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The growing complexity and higher time-to-market pressure make the functional verification of modern large scale hardware systems more challenging. These challenges bring the requirement of a high quality testbench that is capable of thoroughly verifying the design. To reveal a bug, the testbench needs to activate it by stimulus, propagate the erroneous behaviors to some checked points, and detect it at these checked points by checkers. However, current dominant verification approaches focus only on the activation aspect using a coverage model which is not qualified and ignore the propagation and detection aspects. Using a new metric, this paper qualifies the testbench by mutation analysis technique with the consideration of the quality of the stimulus, the coverage model, and the checkers. Then the testbench is iteratively refined according to the qualification feedback. We have conducted experiments on two designs of different scales to demonstrate the effectiveness of the proposed method in improving the quality of the testbench.