The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

Table 6

(a) Ranges of devices geometry and bias conditions for calculation of and for 90 nm and 180 nm CMOS processes. (b) Fitting parameters of monomial expressions of and for 90 nm and 180 nm CMOS processes.

(a)

Parameters	90 nm	180 nm
Gate length	0.09 µm ≤ ≤ 0.45 µm	0.18 µm ≤ ≤ 0.9 µm
Gate width	1 µm ≤ ≤ 100 µm	1 µm ≤ ≤ 100 µm
Overdrive voltage	0.1 V ≤ ≤ 0.4 V	0.1 V ≤ ≤ 0.5 V
Drain to source voltage	0.5 V ≤ ≤ 1.0 V	0.6 V ≤ ≤ 1.2 V

(b)

Parameters	90 nm	180 nm
	0.0423	0.0463
	−0.4578	−0.4489
	0.5275	0.5311
	0.4725	0.4689
	0.0091	0.0096
	−0.5637	−0.5595
	0.5305	0.5194
	0.4695	0.4806