Table of Contents
VLSI Design
Volume 2015, Article ID 540482, 10 pages
Research Article

Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits

Department of Computer Science, Modeling, Electronics and System Engineering, University of Calabria, Via P. Bucci 42C, 87036 Rende, Italy

Received 12 May 2015; Revised 23 September 2015; Accepted 4 October 2015

Academic Editor: Jose Carlos Monteiro

Copyright © 2015 Ramiro Taco et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. To this purpose, a GLBB mirror full adder is implemented by using a commercial 45 nm bulk CMOS triple-well technology and compared to equivalent conventional zero body-biased CMOS and dynamic threshold voltage MOSFET (DTMOS) circuits under different running conditions. Postlayout simulations demonstrate that, at the parity of leakage power consumption, the GLBB technique exhibits a significant concurrent reduction of the energy per operation and the delay in comparison to the conventional CMOS and DTMOS approaches. The silicon area required by the GLBB full adder is halved with respect to the equivalent DTMOS implementation, but it is higher in comparison to conventional CMOS design. Performed analysis also proves that the GLBB solution exhibits a high level of robustness against temperature fluctuations and process variations.