Table of Contents
VLSI Design
Volume 2015, Article ID 540482, 10 pages
http://dx.doi.org/10.1155/2015/540482
Research Article

Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits

Department of Computer Science, Modeling, Electronics and System Engineering, University of Calabria, Via P. Bucci 42C, 87036 Rende, Italy

Received 12 May 2015; Revised 23 September 2015; Accepted 4 October 2015

Academic Editor: Jose Carlos Monteiro

Copyright © 2015 Ramiro Taco et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [7 citations]

The following is the list of published articles that have cited the current article.

  • Ramiro Taco, Itamar Levi, Marco Lanuzza, and Alexander Fish, “Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology,” 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 41–44, . View at Publisher · View at Google Scholar
  • Neha Pannu, and Neelam Rup Prakash, “A power-efficient multiplexer using reversible logic,” Indian Journal of Science and Technology, vol. 9, no. 30, 2016. View at Publisher · View at Google Scholar
  • D. Khalandar Basha, B. Naresh, S. Rambabu, and D. Nagaraju, “Body Biased High Speed Full Adder to LNCS/LNAI/LNBI Proceedings,” Computer Communication, Networking and Internet Security, vol. 5, pp. 81–91, 2017. View at Publisher · View at Google Scholar
  • D Khalandar Basha, V R Sheshagiri Rao, M Rajanikanth, and A Pulla Reddy, “2D symmetric 6T SRAM with reset,” 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings, pp. 348–352, 2017. View at Publisher · View at Google Scholar
  • L. Rekha Shree, Sakthivel, and Kishore Sanapala, “Design of Ultralow Voltage-Hybrid Full Adder Circuit Using GLBB Scheme for Energy-Efficient Arithmetic Applications,” Lecture Notes in Electrical Engineering, vol. 471, pp. 217–223, 2018. View at Publisher · View at Google Scholar
  • D. Khalandar Basha, A. Pulla Reddy, Rollakanti Raju, and G. Srinivas Reddy, “Gated body-biased full adder,” Materials Today: Proceedings, vol. 5, no. 1, pp. 673–679, 2018. View at Publisher · View at Google Scholar
  • Shashikanth Reddy, Khalandar Basha, and Aruna Manjusha, “2D Symmetric16×8 SRAM with reset,” Journal of Engineering and Applied Sciences, vol. 13, no. 1, pp. 58–63, 2018. View at Publisher · View at Google Scholar