A Modularized Noise Analysis Method with Its Application in Readout Circuit Design

Table 4

Comparison with different integration time.

	200 ns	800 ns	3.2 us	12.8 us	51.2 us	204.8 us
Theoretical results	71.5	72.0	72.5	72.9	73.5	75.9
Verilog-A results	74.6	74.4	69.9	75.6	72.8	74.4