A Discrete Event System Approach to Online Testing of Speed Independent Circuits

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/vlsi/volume-2015/651785/figures/651785.fig.0017a.svgz" name="651785.fig.0017a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>State graph</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/vlsi/volume-2015/651785/figures/651785.fig.0017b.svgz" name="651785.fig.0017b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>Output of Petrify</td></tr><tr class="fig-image" id="c"><td><object data="https://static.hindawi.com/articles/vlsi/volume-2015/651785/figures/651785.fig.0017c.svgz" name="651785.fig.0017c" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(c) </b>Output equations of Petrify</td></tr></table>

<div>Screenshot showing the synthesis of DES detector from state graph using Petrify.</div>

VLSI Design

fig17

Figure 17

Figure 17: A Discrete Event System Approach to Online Testing of Speed Independent Circuits 