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VLSI Design
Volume 2015 (2015), Article ID 767161, 7 pages
Research Article

A New CDS Structure for High Density FPA with Low Power

Xiao Wang1,2,3 and Zelin Shi1,3

1Shenyang Institute of Automation, Chinese Academy of Sciences, Shenyang 110016, China
2University of the Chinese Academy of Sciences, Beijing 100049, China
3Key Laboratory of Opto-Electronic Information Processing, Chinese Academy of Sciences, Shenyang 110016, China

Received 21 November 2014; Accepted 22 December 2014

Academic Editor: Jose Silva-Martinez

Copyright © 2015 Xiao Wang and Zelin Shi. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.