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VLSI Design
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Special Issues
VLSI Design
/
2016
/
Article
/
Tab 2
/
Research Article
Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits
Table 2
Area, delay, and dynamic and leakage power of SAED32.28 HVT digital standard cell libraries.
Parameters
AND
OR
XOR
Area (
)
2.033154
2.033152
4.320448
Delay (ns)
0.1
0.06
0.08
Leakage (nW)
297
393
344
Dynamic (nW/MHz)
3
4
2