A Novel Time Synchronization Method for Dynamic Reconfigurable Bus

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/vlsi/volume-2016/5752080/figures/5752080.fig.0010a.svgz" name="5752080.fig.0010a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>Coarse-grain time synchronization results</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/vlsi/volume-2016/5752080/figures/5752080.fig.0010b.svgz" name="5752080.fig.0010b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>Enlarged fine-grain time synchronization results</td></tr></table>

<div>Time synchronization results on real FPGA testbed.</div>

VLSI Design

fig10

Figure 10

Figure 10: A Novel Time Synchronization Method for Dynamic Reconfigurable Bus 