Table of Contents
VLSI Design
Volume 2016, Article ID 6475932, 8 pages
http://dx.doi.org/10.1155/2016/6475932
Research Article

A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs

1Institute of VLSI Design, Hefei University of Technology, Hefei, China
2Department of Electronic Science & Technology, University of Science and Technology of China, 443 Huangshan Road, Hefei, Anhui, China

Received 27 May 2016; Revised 18 August 2016; Accepted 1 September 2016

Academic Editor: Chien-In Henry Chen

Copyright © 2016 Hongmei Chen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A low complexity all-digital background calibration technique based on statistics is proposed. The basic idea of the statistics calibration technique is that the output average energy of each channel of TIADC will be consistent ideally, since each channel samples the same input signal, and therefore the energy deviation directly reflects the mismatch errors of channels. In this work, the offset mismatch and gain mismatch are calibrated by an adaptive statistics calibration algorithm based on LMS iteration; the timing mismatch is estimated by performing the correlation calculation of the outputs of subchannels and corrected by an improved fractional delay filter based on Farrow structure. Applied to a four-channel 12-bit 400 MHz TIADC, simulation results show that, with calibration, the SNDR raises from 22.5 dB to 71.8 dB and ENOB rises from 3.4 bits to 11.6 bits for a 164.6 MHz sinusoidal input. Compared with traditional methods, the proposed schemes are more feasible to implement and consume less hardware resources.