Table of Contents
VLSI Design
Volume 2016, Article ID 8093614, 16 pages
Research Article

A Cache System Design for CMPs with Built-In Coherence Verification

1Department of Computer Science and Engineering, National Institute of Technology Durgapur, West Bengal 713209, India
2Department of Computer Science and Technology, Indian Institute of Engineering Science and Technology Shibpur, West Bengal 711103, India

Received 22 December 2015; Revised 19 May 2016; Accepted 24 May 2016

Academic Editor: A. Postula

Copyright © 2016 Mamata Dalui and Biplab K. Sikdar. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This work reports an effective design of cache system for Chip Multiprocessors (CMPs). It introduces built-in logic for verification of cache coherence in CMPs realizing directory based protocol. It is developed around the cellular automata (CA) machine, invented by John von Neumann in the 1950s. A special class of CA referred to as single length cycle 2-attractor cellular automata (TACA) has been planted to detect the inconsistencies in cache line states of processors’ private caches. The TACA module captures coherence status of the CMPs’ cache system and memorizes any inconsistent recording of the cache line states during the processors’ reference to a memory block. Theory has been developed to empower a TACA to analyse the cache state updates and then to settle to an attractor state indicating quick decision on a faulty recording of cache line status. The introduction of segmentation of the CMPs’ processor pool ensures a better efficiency, in determining the inconsistencies, by reducing the number of computation steps in the verification logic. The hardware requirement for the verification logic points to the fact that the overhead of proposed coherence verification module is much lesser than that of the conventional verification units and is insignificant with respect to the cost involved in CMPs’ cache system.