Table of Contents
VLSI Design
Volume 2016, Article ID 8093614, 16 pages
http://dx.doi.org/10.1155/2016/8093614
Research Article

A Cache System Design for CMPs with Built-In Coherence Verification

1Department of Computer Science and Engineering, National Institute of Technology Durgapur, West Bengal 713209, India
2Department of Computer Science and Technology, Indian Institute of Engineering Science and Technology Shibpur, West Bengal 711103, India

Received 22 December 2015; Revised 19 May 2016; Accepted 24 May 2016

Academic Editor: A. Postula

Copyright © 2016 Mamata Dalui and Biplab K. Sikdar. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Mamata Dalui and Biplab K. Sikdar, “A Cache System Design for CMPs with Built-In Coherence Verification,” VLSI Design, vol. 2016, Article ID 8093614, 16 pages, 2016. https://doi.org/10.1155/2016/8093614.