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VLSI Design
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Special Issues
VLSI Design
/
2016
/
Article
/
Tab 1
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Research Article
A Cache System Design for CMPs with Built-In Coherence Verification
Table 1
Next state functions.
PS
111
110
101
100
011
010
001
000
Rule
RMT
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
ā
NS
1
1
1
1
1
1
1
1
254
NS
1
1
1
1
1
1
1
0
255