A Cache System Design for CMPs with Built-In Coherence Verification

Table 2

Cache sharing vector update.

Current sharing vector	Event	Desired sharing vector	Faulty sharing vector	Fault effect	Cases
(1)	(2)	(3)	(4)	(5)	(6)
All p’s are 0s	reads	p is 1 and all others are 0s	All p’s are 0s	Faulty (F)	Case 1
			p is 1 and all others are 0s	Faulty (F)	Case 2
	writes	p is 1 and all others are 0s	All p’s are 0s	Faulty (F)	Case 1
			p is 1 and all others are 0s	Faulty (F)	Case 2
All p’s are 1s	writes	p is 1 and all others are 0s	p is 1 and all others are 0s	Faulty (F)	Case 2
			p  & p are 1 and others are 0s	Faulty (F)	Case 3
			p is 1 and others are 1s & 0s	Faulty (F)	Case 3
p’s are 1s & 0s	reads	p is 1 and all others are 1s & 0s	p is 0 and others are 1s & 0s	Faulty (F)	Case 1
	writes	p is 1 and all others are 0s	p is 1 and others are 1s & 0s	Faulty (F)	Case 3
p is 1 and all others are 0s	writes	p is 1 and all others are 0s	p  & p are 1 and others are 0s	Faulty (F)	Case 3