A Cache System Design for CMPs with Built-In Coherence Verification

Table 5

Parameters used in full system simulation.

Parameter	Value
Processors	x86 cores, 1 GHz, single issue, in-order
cache	64 KB per core, unified, LRU replacement policy
	4-way associative, -cycle latency, -byte line
cache	2 MB, LRU replacement policy, -way associative, 20-cycle latency, 64-byte line
Memory	1 GB, 100-cycle latency
Network	2D mesh topology, -cycle router, 1-cycle link latency, 36 bytes wide