A Cache System Design for CMPs with Built-In Coherence Verification

Table 9

Hardware requirements for high-speed design ().

Number of cores	Number of FFs	Number of NANDs	Number of XORs	Area (units)	Area (units)
(1)	(2)	(3)	(4)	(5)	(6)
16	16	144	16	259840	259840
32	32	288	32	519680	519680
64	64	540	64	1039360	1039360
128	128	1152	128	2078720	2078720
256	256	2304	256	4157440	4157440