Table of Contents
VLSI Design
Volume 2016, Article ID 8787919, 12 pages
http://dx.doi.org/10.1155/2016/8787919
Research Article

FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW

1Institute of Microelectronics, Tsinghua University, Beijing 100084, China
2School of Software, Beijing Institute of Technology, Beijing 100081, China
3College of Information Engineering, Capital Normal University, Beijing 100048, China

Received 12 June 2016; Revised 4 October 2016; Accepted 19 October 2016

Academic Editor: Jose Carlos Monteiro

Copyright © 2016 Yumin Hou et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper proposes FuMicro, a fused microarchitecture integrating both in-order superscalar and Very Long Instruction Word (VLIW) in a single core. A processor with FuMicro microarchitecture can work under alternative in-order superscalar and VLIW mode, using the same pipeline and the same Instruction Set Architecture (ISA). Small modification to the compiler is made to expand the register file in VLIW mode. The decision of mode switch is made by software, and this does not need extra hardware. VLIW code can be exploited in the form of library function and the users will be exposed under only superscalar mode; by this means, we can provide the users with a convenient development environment. FuMicro could serve as a universal microarchitecture for it can be applied to different ISAs. In this paper, we focus on the implementation of FuMicro with ARM ISA. This architecture is evaluated on gem5, which is a cycle accurate microarchitecture simulation platform. By adopting FuMicro microarchitecture, the performance can be improved on an average of 10%, with the best performance improvement being 47.3%, compared with that under pure in-order superscalar mode. The result shows that FuMicro microarchitecture can improve Instruction Level Parallelism (ILP) significantly, making it promising to expand digital signal processing capability on a General Purpose Processor.