VLSI Design

CAD for Gigascale SoC Design and Verification Solutions


Publishing date
15 Apr 2011
Status
Published
Submission deadline
15 Dec 2010

Lead Editor
Guest Editors

1Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, MI 49931, USA

2Institute of Microelectronics, Tsinghua University, Beijing 100084, China

3IBM Austin Research Lab, Austin, TX 78759, USA


CAD for Gigascale SoC Design and Verification Solutions

Description

As VLSI technology enters the nanometer regime, the design complexity is rapidly increasing with timing, power, routability, and reliability. Salient design automation techniques for scalable SoC design and verification solutions that could greatly improve the design quality are highly desired.

This special issue is dedicated to the research problems in all aspects of System-on-Chip (SoC) implementation and verification. New optimization, simulation, and verification techniques containing theoretical and/or applied contributions that emphasize the scalability to future large designs are all welcome. This special issue will become an international forum for researchers to summarize the state-of-the-art development in scalable VLSI design and verification algorithms and methodologies. Topics of interest include, but are not limited to:

  • Physical synthesis (interconnect optimization, buffer insertion, gate sizing, vt assignment, layer assignment, etc.)
  • Floorplanning and placement
  • Routing (congestion analysis, global and detail routing techniques)
  • Clock synthesis
  • Design for manufacturability and variability
  • Functional and formal verification
  • System level modeling and simulation
  • Electronic System Level (ESL) design methodologies, tools, languages, and flow
  • Low Power-aware systems design and verification
  • 3D VLSI/NoC design and verification flow/synthesis
  • ASIC emulation and FPGA prototyping
  • IP specification, creation, and reuse
  • New ATPG and DFT solutions

Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/vlsi/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable:


Articles

  • Special Issue
  • - Volume 2011
  • - Article ID 398390
  • - Editorial

CAD for Gigascale SoC Design and Verification Solutions

Shiyan Hu | Zhuo Li | Yangdong Deng
  • Special Issue
  • - Volume 2011
  • - Article ID 896241
  • - Research Article

Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

I. Hameem Shanavas | Ramaswamy Kannan Gnanamurthy
  • Special Issue
  • - Volume 2011
  • - Article ID 756561
  • - Research Article

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

Usha Mehta | K. S. Dasgupta | N. M. Devashrayee
  • Special Issue
  • - Volume 2011
  • - Article ID 328640
  • - Research Article

Efficient Resource Sharing Architecture for Multistandard Communication System

T. Suresh | K. L. Shunmuganathan
  • Special Issue
  • - Volume 2011
  • - Article ID 892310
  • - Research Article

Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies

M. A. R. Chaudhry | Z. Asad | ... | J. Hu
  • Special Issue
  • - Volume 2011
  • - Article ID 845957
  • - Research Article

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

Yoni Aizik | Avinoam Kolodny
  • Special Issue
  • - Volume 2011
  • - Article ID 731957
  • - Review Article

SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection

Debasri Saha | Susmita Sur-Kolay
  • Special Issue
  • - Volume 2011
  • - Article ID 471903
  • - Review Article

The Impact of Statistical Leakage Models on Design Yield Estimation

Rouwaida Kanj | Rajiv Joshi | Sani Nassif
  • Special Issue
  • - Volume 2011
  • - Article ID 503025
  • - Review Article

Shedding Physical Synthesis Area Bloat

Ying Zhou | Charles J. Alpert | ... | Louise H. Trevillyan
  • Special Issue
  • - Volume 2011
  • - Article ID 948926
  • - Review Article

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

Usha Mehta | Kankar Dasgupta | Niranjan Devashrayee

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