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Active and Passive Electronic Components

Volume 2012 (2012), Article ID 871620, 8 pages

http://dx.doi.org/10.1155/2012/871620

## Multilayer, Stacked Spiral Copper Inductors on Silicon with Micro-Henry Inductance Using Single-Level Lithography

Sibley School of Mechanical and Aerospace Engineering, Cornell University, Ithaca, NY 14853, USA

Received 16 June 2011; Revised 16 January 2012; Accepted 23 January 2012

Academic Editor: Egidio Ragonese

Copyright © 2012 Timothy Reissman et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

We present copper structures composed of multilayer, stacked inductors (MLSIs) with tens of micro-Henry inductance for use in low frequency (sub 100 MHz), power converter technology. Unique to this work is the introduction of single-level lithography over the traditional two-level approach to create each inductor layer. The result is a simplified fabrication process which results in a reduction in the number of lithography steps per inductor (metal) layer and a reduction in the necessary alignment precision. Additionally, we show that this fabrication process yields strong adhesion amongst the layers, since even after a postprocess abrasion technique at the inner diameter of the inductors, no shearing occurs and connectivity is preserved. In total, three separate structures were fabricated using the single-level lithography approach, each with a three-layered, stacked inductor design but with varied geometries. Measured values for each of the structures were extracted, and the following results were obtained: inductance values of 24.74, 17.25, and 24.74 *μ*H, self-resonances of 9.87, 5.72, and 10.58 MHz, and peak quality factors of 2.26, 2.05, and 4.6, respectively. These values are in good agreement with the lumped parameter model presented.

#### 1. Introduction

Over the last decade, researchers have done a considerable amount of work to model, characterize, and design air-core spiral inductors on silicon technology for both radio-frequency integrated circuits (RFIC) and monolithic microwave integrated circuits (MMICs). In most of these works, both performance and cost are typical issues examined. For many designers, performance relates directly to improving the quality factor of these spiral inductors. Most notably, this has been achieved using designs such as multilayered, stacked inductors (MLSIs), see Figure 1, which increase the inductance value due to the mutual magnetic coupling [1], and multiple shunt inductors, which lower the resistance [2, 3]. For those researchers concerned with cost, much of the focus is within analyzing the process with respect to the standard complementary metal oxide semiconductor (CMOS) technology, where the key factors in determining the cost are (1) feature size, (2) number and kinds of layers, and (3) chip area occupied [4]. Within this work, we focus on simplifying the fabrication of integrated inductors for the emerging area of power converter technology. Specifying for this growing field, researchers must again balance performance and cost issues with new requirements like the need for much higher inductance in the order of micro-Henries and operation ranges below 100 MHz.

To highlight some examples of the balance of performance and cost issues, we cite here results of recent research within short-range radio frequency identifier (RFID) antennas, and DC/DC converters. For wireless technology, a typical approach of biomedical devices [5] and strain sensors [6] has been for researchers to use large, single in-plane inductors as short-range RFIDs. Thus they have chosen to balance the simplicity of single-layer inductor design with the cost of using large chip areas, which for [5, 6] yield 2.7 cm diameters in order to meet the 4-5 *μ*H inductance requirements. For DC-DC converter technology, researchers have chosen to modify the single-layer CMOS fabrication by orienting the final structure orthogonal to the substrate using magnets and a hinge design, known as plastic deformation magnetic assembly (PDMA) [4]. The results are structures with 1 *μ*H inductance and a small chip area (0.1 mm × 0.1 mm), but with the increased types of layers adding cost and difficulty.

In this work, we introduce a simplified CMOS fabrication approach using single-level lithography in order to reduce the difficulty of the number of lithographic steps per layer over the traditional two-level lithographic approach. This simplified layer approach allows us to then extend the number of layers from a single-layer design to a MLSI design at a lower cost over the traditional approach. To substantiate the selection of the multilayer over single-layer design option, we compared, based on cost factors, several works aimed at achieving high-inductance monolithic inductors. From that review, we found that higher inductance, single-layer inductors were achieved using exotic substrates [7, 8], while MLSI on standard, silicon substrates [1, 9] were able to achieve similar, if not higher, inductance values, by exploiting the mutual magnetic coupling effects. When examining the results with respect to the factors for cost, the latter is seemingly better, especially with respect to increased inductance per unit area, and without the need for deviation from standard CMOS processes. By combining our simplified single-level lithography design, which features potential for decreased cost per inductor layer, with a multilayer process, which increases cost, the resulting reduction in chip area should provide a net cost advantage. Thus, we detail our simplified fabrication technique with respect to the standard two-level lithography approach to highlight the differences. In addition, we analyze the performance metrics of three structures fabricated using our single-level lithography approach, recording the inductance value, , the inductance per unit area, the quality factor, , and the self-resonance frequency, SRF, so as to allow researchers to compare both performance and cost with future works. Lastly, we include a lumped parameter analytical model of the multilayer, stacked inductor so as to validate the measured results.

#### 2. Multilayered, Stacked Spiral Inductor Theory

When designing single-layer, spiral inductors, typically a lumped parameter approximation using the *π*-type electrical model [10–13] is applied for simplicity, which is valid up to the self-resonance frequency, see Figure 2. This model can be viewed as an RLC circuit, where the inductance, , and capacitance, , of the coil are in parallel, with losses to the substrate induced by the capacitive and conductive properties of the substrate. These and other parasitic losses vary with respect to the geometry and orientation of the inductor. Techniques for predetermining all of these parameters’ values have ranged from empirical expressions [12] to Greenhouse’s method [11] to electromagnetic field solvers [14].

Using this model, various geometries and materials have been studied within the literature to reduce the losses and produce higher performance metrics. Specifically, some researchers have experimented with various substrate materials, Quartz, GaAs, and Sapphire [7, 8, 15], to reduce the losses brought on by the and components. Researchers have also experimented with creating large trenches on the underside of the devices to increase the separation distance to the substrate and reduce the capacitive loss [16]. While these techniques are valid, they add considerable complexity and cost to the fabrication process, since they introduce costly materials and require long etching process times.

While the reduction of losses has shown improvement in inductor performance, large inductance variation can occur by manipulation of the inductor geometry itself [10]. We estimate the inductance of an in-plane spiral using the zeroth order approximation given by a current sheet expression [12]. Equation (1) assumes a nonferrous core, which results in the inductance being determined exclusively by the spiral geometry. We define as the permeability, as the number of turns, as the average diameter of the turns, and as the fill ratio of the single-layer spiral. The coefficients are dependent on the layout of the spiral, such as square, hexagonal, octagonal, or circular. To increase the inductance value of single-layer spirals, increasing the number of turns, or , is a simple and effective option.

To increase the inductance values without further increasing the footprint area, we expand the single-layer spiral to a multilayered, stacked spiral. MLSI spirals have been shown in the literature to increase single-layer spiral inductance values by the summation of the individual single-layer spiral inductances and their mutual inductances between layers [3, 4]. The equivalent inductance, , for a MLSI is shown in [12] The value is the number of stacked layers, the term refers to the th single-layer spiral inductance value, and the term accounts for the mutual inductance between each set of single-layer spirals. If we assume that the inductance of each single-layer spiral is approximately the same, then (2) reduces to the inductance of a single-layer spiral times the square of the number of stacked spiral layers. Thus, by interconnecting the spirals, we can increase the inductance of each MLSI design by a square of the number of single-layer spiral turns and multiply that value by a square of the number of stacked spiral layers.

However, predicting only the inductance does not give an accurate estimate for the resultant reactance, or nominal inductance, of the integrated inductor measured using impedance analysis. For the reactance, a relationship between the capacitance and the resistance of the device is needed as well. A general form for calculating the capacitance of two adjoining surfaces is shown in The term is the permittivity of the medium, and the term is the separation distance between the two facing surface areas, . By increasing the number of turns for a single-layer spiral, the area and capacitance also increase. To lower the capacitance while increasing the inductance, multilayered, stacked, spirals have the following equivalent capacitance, see Figure 3 [1] Equation (4) is derived from the assumption that there exists perfect coupling between each two inductive elements, and thus the voltages in each turn are equal. The term is then simply expressed as the capacitance between each of the single-layer spiral layers, which is determined by the dielectric layers in between. It is determined from (4) that MLSI design lowers the effect that the substrate has on the total capacitance when compared to single-layer inductors. In addition, the introduction of large separation distances between each single-layer spiral layer, using interconnect technology [17, 18], can further reduce the equivalent capacitance and increase the SRF.

To complete the lumped parameters, the series resistance is found using where is the conductance of the inductor’s metal trace, is the total length of the spiral inductors, and is the effective cross-sectional area of the inductor’s metal trace. At zero frequency, or DC, the effective cross-sectional area is the physical cross-sectional area of the inductor’s trace. For low frequency designs, it can be assumed that the DC resistance is a good estimate of the actual resistance, as long as the proximity effects and skin depth effects, while present, are orders of magnitude less than the DC resistance [19].

Combining (2), (4), and (5), the MLSI shown in Figure 1 has a reactance, of [20] The term refers to the operational frequency of the inductor. Equation (6) approximates the MLSI as a LC circuit in parallel with a finite resistance. Thus, the self-resonance frequency, SRF, is when the reactance value is equal to zero. To increase the nominal inductance, or reactance, and the useful operation range, or SRF, it is clear that maximizing the inductance and minimizing the capacitance are the key aspects of the design. MLSI are thereby an excellent choice for high inductance devices, as both inductance and capacitance can be tailored with geometric parameters.

A final inductor performance metric to estimate is the value of the quality factor, or . The is a measure of the ratio of the energy stored over the energy lost in one cycle. A simple expression for the can be estimated up to the SRF using the relationship for the resistance, (5), and the reactance, (6) Therefore, to increase the value for these low frequency devices, the length of the trace, which is increasing with every single-layer turn or number of stacked layers, must be offset by a larger trace width and/or thickness. Both single- and multilayered, stacked inductors have the advantage that both the trace width and the thickness can easily be modified to larger values by creating a larger patterning mold [18].

By using the performance metric relationships listed, we have generated theoretical predictions for the measured reactance (nominal inductance), the resistance, the first self-resonance frequency, and the quality factor of MLSI. We have also shown the key geometrical considerations associated with creating high inductance and high . With the lumped parameter model established, we now focus on a how single-level lithography can lower the fabrication cost for these MLSI designs.

#### 3. Device Fabrication

A major cost concern with CMOS fabrication is keeping the number of steps or processes involved, as well as the precision needed within each step, to a minimum. In accordance with these principles, to fabricate a multilayer, stacked copper inductor, we use a single-level lithography process as opposed to the traditional two-level lithographic process. To achieve this simplified process, we use two types of photo-resists, SU-8 and SPR-220. SU-8 is a permanent photo-resist that serves as a structural layer to build the coil layers onto, as well as the dielectric material between the layers. SPR-220 is then used after evaporating the copper inductor layer to pattern the inductor using wet-etching. Thus, unlike two-level lithography, single-level lithography eliminates the step of electroplating the patterned inductor layer. After the single-level lithography is finished, holes for interconnects between the stacked inductor layers are made on the SU-8 layer and filled with copper using electroplating. These copper connects create a conductive pathway from the seed layer to the first planar inductor and each subsequent planar inductor layer. By repeating these two processes, inductor layers can be stacked onto previous layers and the trace is able to maintain its connectivity through the connection holes. Thus, the entire process eliminates a lithographic step for each inductor layer, reducing the fabrication cost over two-level lithography. Lastly, we include an extremely fast process, abrasion drilling, as a way of creating an air core once the MLSIs are completed.

Figure 4 shows a simplified version of our process. First, a silicon wafer is thermally oxidized to create an insulator between the silicon substrate and the inductor structure, reducing the parasitic substrate loss, Figure 4(a). Next, a tantalum layer is evaporated onto the wafer to improve the adhesion of subsequent evaporated layer, the coil’s copper seed layer. The seed layer provides a pathway for electroplating the deep interconnects, Figure 4(b). On top of the seed layer, SU-8 2010 photo-resist solution is spun at a specified thickness, which determines the thickness of the dielectric layer (relative permittivity of 2.46), or the separation distance to the first spiral inductor layer and the resultant capacitance, . We pattern the SU-8 with a standard lithography process using the connecting layer mask in order to define the interconnect position. By creating only a single, large interconnect, the precision for alignment of the spiral layer is lowered, reducing the difficulty of the lithography process. A final annealing step, of 115°C for 2 minutes, is applied after developing, to improve the adhesion of the SU-8 and copper inductor layers. When the wafer is dried, it is descummed with oxygen plasma etching, which increases the surface roughness, and assists the adhesion of the next copper layer, Figure 4(c).

To build each inductor layer, copper is evaporated over the entire area of the wafer at a rate less than 20 Angstroms per second, Figure 4(d). Next, P20 is spun to assist with the adhesion of the patterning layer, which is SPR220-7. Using a negative coil mask and a standard lithography process, the SPR220 is used to form an outline covering the in-plane spiral pattern, Figure 4(e). To remove the excess copper, the wafer is immersed in a copper etchant and careful attention is made to not agitate the solution, otherwise coil liftoff can occur. When the complete copper removal is visually observed, the wafer is taken out and thoroughly washed with distilled water. The area covered with SPR220 is left as the in-plane patterned inductor spiral, and the SPR220 is removed with a gentle spraying of acetone and then isopropanol, Figure 4(f). By doing the patterning of each in-plane spiral this way, we reduce the number of steps needed to only a single-level patterning and concurrently require only a low precision of the pattern be necessary for achieving alignment with the interconnect points between the layers, since the feature sizes are large for micro-Henry inductance. This process is significantly less difficult to achieve than most electroplating techniques used to produce coils, which require a two-level patterning lithography [18]. To explain further, in the two-level patterning, after the evaporation and patterning of the inductor, another level of photo-resist is needed in order to create channels for allowing electroplating of the inductor layer to increase the in-plane thicknesses. While larger thicknesses do reduce the series resistance, the process adds another step for every inductor layer as well as it introduces the possibility of needing to do chemical metal polishing (CMP) in order to form parallel layers for future mask alignments. So by using our single-level lithography we trade off constraining the thickness, and the resistance, of the inductor to the limits prescribed by the evaporation process in order to reduce the fabrication cost. In applications like power converter technology, this performance tradeoff is not as critical, since the high inductance values offset the high resistance, yielding reasonable values. To complete the process and make all the layers mutually conductive, we use the standard procedure of electroplating the interconnect layers.

In this step, we electroplate copper in a copper sulfate solution, Microfab SC from Enthone, Inc., at a current density of 0.02 mA/mm^{2} to connect the copper in-plane spiral layer to the copper seed layer using the interconnect holes (Figure 4(g)). The rate and duration at which the electroplating process occur are dependent on the concentration of the electroplating solution and the amount of copper that needs to be deposited within the interconnect, that is, the amount needed to both fill the hole and make an electrical connection between the inductor layers. For our procedure, this electroplating process is simplified, because it requires only an electrical connection between the electroplating circuit’s clips and the seed layer, which is exposed at the edge of the wafer. With an electrical connection to the seed layer, current flow and copper deposition within the interconnect are easily achieved. Once the first interconnect is filled, continuity to the inductor layer is achieved. We are therefore able to verify completion of this process by solely checking that continuity exists.

The two processes are then repeated from the SU-8 spinning, Figure 4(c), to the copper interconnect between the copper inductor layers (Figure 4(g)), forming a MLSI design, Figure 4(h). For the electroplating process, once an interconnect makes continuity with the next inductor layer, the current will continually flow to the next interconnect. This continues until the electroplating process deposits copper within the last interconnect and makes a connection to the uppermost inductor layer. Since MLSIs need to have current flow in the same direction for all the inductor layers, in order to superimpose inductance effects, a total of four masks, two for alternating connecting layer masks and two for alternating coil layer masks, are needed. To summarize, our entire procedure requires a single-level, low-precision lithography, and one simple continuity test to be passed after the electroplating process for each inductor layer of a MLSI design. We can conclude that the entire fabrication procedure meets many of the attributes considered for low difficulty and low cost.

Lastly, a final postprocessing step is performed that uses a simple, fast method for creating air cores within these MLSIs. The technique is an abrasion, or manual drilling process, in which we use a blunt, diamond-coated drill bit, sized to a diameter smaller than the inductor’s inner diameter, to create a through hole at the center, Figure 4(i). By applying light hand pressure using a microdrill and manually turning the drill bit, a hole is created in the inner diameter of the multilayer coil within seconds (see Figure 5), which is far faster than etching techniques previously used in the literature for creating cavities [1]. In addition to the improvement on time, this step shows that with our fabrication technique, the single-level lithography provides adequate adhesion and support to maintain the inductor’s structural integrity and electrical connectively even under abrasion, bending, and shear forces.

Figure 6 shows an overhead view of a MLSI fabricated using our single-level lithography process and with the inner core removed by the abrasion process. Each hash mark in the overhead scale depicts 500 *μ*m increments. Figure 7 shows a cross-sectional cut of the same inductor in Figure 6, where the sections of light gray matter are the copper coil layers, and the dark gray matter is the SU-8 dielectric layers.

#### 4. Device Characterization and Results

Using our single-level lithography technique, we fabricated three MLSI designs (each with 3 inductor layers in series) with varying trace widths, trace thicknesses, and spacing between inductor layers (see Table 1). Each of the MLSIs were designed to have a nominal inductance value close to 20 *μ*H. Measurements were conducted for each design to verify the nominal inductance as well as to observe the effects of the geometric variations on performance metrics such as nominal inductance per footprint area, resistance, quality factor, and SRF. Measurements were performed using a HP4194 impedance analyzer and on-chip cascade probes, with averaging of the two-port -parameters of the inductors from 150 kHz to 15 MHz frequency range. Averages were performed using 401 sample points distributed linearly over the frequency range, with 32 trials at each frequency point. Pad capacitance was deembedded by subtracting out the open-circuit structure -parameters from the spiral -parameters. The calibration procedure we used is the standard approach and is reported widely [14].

We observed general agreement between our lumped parameter model and our experimental results for nearly all performance metric values (see Figure 8 and Table 2). The only exception was the prediction for the maximum of Design 1, which has an unusually flat curve over its measured range. Since all other predictions lie within acceptable experimental results, less than 15%, we assume the model is an accurate first-order approximation up to the first self-resonance frequency. Here we note that Table 2 shows that the lumped parameter model is particularly useful for designing the nominal inductance values of these devices to the desired 20 *μ*H inductance value. To explain, the nominal inductance reported in Table 2 is defined as the linear slope of the reactance and the corresponding frequency, , between an initial value in the low frequency range and a final value before the SRF
Thus, by designing the SRF higher than the intended operating range, we are able to confirm the nominal inductance is achieved for all three designs, using an intermediate frequency evaluation of 1 MHz.

To understand the fabrication implications of the geometric variations, we compare specific performance metrics such as the , SRF, and volume. With Design 1 as a baseline, Design 2 increases the trace thickness by 50% for each inductor layer and the trace width by 30%. These changes reduce the resistance by nearly one-half the value compared to Design 1, but result in a longer evaporation time for each inductor layer. To compensate, we reduce the inductor’s volume by reducing the thickness of the SU-8 layer, the dielectric layer between the stacked inductors, to one-third its original value, which lowers the electroplating time for each interconnect layer. However, lowering the separation distance between the inductor layers increases the capacitance and reduces the SRF. The result is a design with a slight decrease in fabrication time at one-half the volume, but at the expense of lowered performance values for all values (nominal inductance, nominal inductance per footprint area, , and SRF) except the resistance. Focusing on improving the performance metrics with minor expense to the fabrication process, Design 3 uses the same SU-8 (dielectric) layer thickness between inductor layers and the same inductor pattern as Design 1, but increases the trace thickness of each inductor layer to twice the value. The result is a reduction of the resistance by one-half but at the expense of nearly doubling the evaporation time for each inductor layer. While this is a slight fabrication disadvantage, major performance metrics can be achieved such as increasing the to twice the value of Design 1, maintaining the nominal inductance, and slightly extending the SRF. Thus, from this small parametric analysis, we are able to compare the variation in performance metrics and fabrication for changes in the geometry of these high-inductance devices as well as show the accuracy of our lumped parameter model.

When comparing these results to the literature [1, 9], these MLSI stand in an inductance class entirely by themselves. Previous researchers focused on maintaining SRF values close to or within the GHz range to allow for RF applications and resulted in inductance values limited to hundreds of nano-Henries. Our devices demonstrate tens of micro-Henries inductance and maintain factors at 2 to 4.6. Through optimization, a balance in designs for appropriate inductance, self-resonance, and could be made. Thus this new class of inductors demonstrates useful lumped-parameter modeling and a simplified fabrication process for achieving these performance metrics as well as potentially reduced cost.

#### 5. Conclusions

Given the need for high-inductance devices in power converter technology, our main goal in this work was to simplify the CMOS process while increasing the performance of MLSI devices for low frequency range operation. We found that to achieve micro-Henry inductance values, the MLSI design required a balance between a large number of turns per inductor layer and a large number of stacked inductor layers. In addition, to lower the manufacturing difficulty to achieve such a design, a reduction in the number of lithographic steps, as well as an increase in feature size, was critical. Key points include the use of a single-level patterning for the lithography of each inductor layer, and the creation of large interconnects via an electroplating process, which allows for a low required alignment between spiral layers. The large interconnect (dielectric) layers also preserve the large nominal inductance values by reducing the capacitive effect. Finally, a fast abrasion drilling method was implemented to create air cores, which reduces the time required to produce the cavity to mere seconds and represents a significant time savings compared to etching. Together, this simplified approach results in a low cost fabrication method for micro-Henry inductance integrated inductors. In summary, the single-level lithography fabrication process in conjunction with MLSI designs produced devices exhibiting performance and cost metrics for improving existing power converter technology.

#### Acknowledgments

The authors would like to thank the financial support provided by the DARPA Microsystems Technology Office HiMEMS Program through the Boyce Thompson Institute for Plant Research under the supervision of Dr. Amit Lal. They would also like to acknowledge that this work was performed in part at the Cornell NanoScale Facility, a member of the National Nanotechnology Infrastructure Network, which is supported by the National Science Foundation (Grant ECS-0335765).

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