VLSI Design

Advanced VLSI Architecture Design for Emerging Digital Systems

Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing

High-Efficient Circuits for Ternary Addition

Engineering Change Orders Design Using Multiple Variables Linear Programming for VLSI Design

Design of Smart Power-Saving Architecture for Network on Chip

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design

Parallel Jacobi EVD Methods on Integrated Circuits

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Gate-Level Circuit Reliability Analysis: A Survey

High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos

Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity

VLSI Architectures for Image Interpolation: A Survey

Radix-2^α/4^β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

VLSI Design

Table of Contents

Table of Contents: 2014

Advanced VLSI Architecture Design for Emerging Digital Systems

Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing

High-Efficient Circuits for Ternary Addition

Engineering Change Orders Design Using Multiple Variables Linear Programming for VLSI Design

Design of Smart Power-Saving Architecture for Network on Chip

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design

Parallel Jacobi EVD Methods on Integrated Circuits

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Gate-Level Circuit Reliability Analysis: A Survey

High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos

Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity

VLSI Architectures for Image Interpolation: A Survey

Radix-2^α/4^β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

VLSI Design

Table of Contents

Table of Contents: 2014

Advanced VLSI Architecture Design for Emerging Digital Systems

Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing

High-Efficient Circuits for Ternary Addition

Engineering Change Orders Design Using Multiple Variables Linear Programming for VLSI Design

Design of Smart Power-Saving Architecture for Network on Chip

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design

Parallel Jacobi EVD Methods on Integrated Circuits

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Gate-Level Circuit Reliability Analysis: A Survey

High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos

Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity

VLSI Architectures for Image Interpolation: A Survey

Radix-2α/4β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

Radix-2^α/4^β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation