Recently a novel clock distribution scheme called Branch-and-Combine(BaC) has been proposed. The schemeguarantees constant skew bound irrespective of the size of the clocked network. It utilizes simple nodes to processclock signals such that clock paths are adaptively selected to guarantee constant skew bound. The paper uses aVLSI model to compare the properties of the new scheme to those of the well established H-Tree approach. TheH-Tree is a binary tree of simple buffers which is laid out such that leaves are at equal distances from the root.Our study considers clocking 2-D processor meshes of arbitrary sizes. We evaluate and compare the relevantparameters of both schemes in a VLSI layout context. We utilize parameters such as clock skew, link costs, nodecosts and area efficiency as the basis for comparison. We show that for each BaC network, there is a certainthreshold size after which it outperforms the corresponding tree network in terms of skew. We also show thatexcept for node costs, BaC networks outperform the H-Tree, especially when the size of the clocked network islarge. As an extension we show that BaC clocking does not suffer from potential pulse disappearance, no matterhow large the network is.

Ahmed   El-Amawy

Umasankar   Maheshwar

A Comparative Study of SynchronousClocking Schemes for VLSI Based Systems

A formal approach for the transformation of computation intensive digital signal processing algorithms intosuitable array processor architectures is presented. It covers the complete design flow from algorithmic specificationsin a high-level programming language to architecture descriptions in a hardware description language. Thetransformation itself is divided into manageable design steps and implemented in the CAD-tool DECOMP whichallows the exploration of different architectures in a short time. With the presented approach data independentalgorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology forarray processor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences.The implementation of the formal approach in the DECOMP is an important step towards designautomation for massively parallel systems.

Uwe  Vehlies

Stepwise Transformation of Algorithmsinto Array Processor Architecturesby the DECOMP

Bit parallel and bit serial VLSI designs for performing 1-dimensional Discrete Cosine Transforms are compared,in terms of size, complexity and throughput. It is concluded that the bit serial approach is more suited to thisapplication, given the limitations of not only the available VLSI design tools, but also the available silicon realestate allocated for final chip fabrication.

David   Crook

John  Fulcher

A Comparison of Bit Serialand Bit Parallel DCT Designs

We propose efficient heuristics for placing input/output (I/O) pads around the VLSI chip boundary. Theheuristics are based on the circuit connectivity and do not require the placement of cells. This is useful for cellplacement methods that require the knowledge of I/O pad placement. Using these heuristics, several padplacement candidates can be generated as input to cell placement algorithms.

Khaled  Al-Zamel

Mukkai S. Krishnamoorthy

Input/Output Pad Placement Problem

A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believedwithin the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex.This conclusion is based on a simplified linear RC model to predict gate delays. In the proposed optimizationalgorithm, a nonlinear, non-RC based transistor delay model was used which resulted in a non-convex relationshipbetween the delay and the silicon area of a VLSI chip. Genetic algorithms are better suited for discrete,non-convex, non-linear optimization problems than traditional calculus-based algorithms. By using the geneticalgorithms in the performance and area optimization, we are able to find the optimal values for both delay andsilicon area for the ISCAS benchmark circuits.

Xiao-Dong  Wang

Tom   Chen

Performance and Area Optimization of VLSISystems Using Genetic Algorithms

We show that obtaining the optimal orientations of modules to minimize the length of the longest wire isNP-hard. If each module is permitted only two possible orientations, this can be done in linear time. When allfour orientations are permissible and wires are restricted to connect modules whose separation is bounded bysome constant, the problem also can be solved in linear time.

Kyunrak  Chong

Sartaj  Sahni

Flipping Modules to MinimizeMaximum Wire Length

We derive some properties of the star graph in this paper. In particular, we compute the number of nodes at distance ifrom a fixed node e in a star graph. To this end, a recursive formula is first obtained. This recursive formula is,in general, hard to solve for a closed form solution. We then study the relations among the number of nodes atdistance i to node e in star graphs of different dimensions. This study reveals a very interesting relation amongthese numbers, which leads to a simple homogeneous linear recursive formula whose characteristic equation iseasy to solve. Thus, we get a systematic way to obtain a closed form solution with given initial conditions for anyfixed i.

Ke  Qiu

Selim G. Akl

On Some Properties of the Star Graph

A central problem in building large scale parallel machines is the design of the interconnection network. Interconnectionnetwork design is largely constrained by packaging technology. We start with a generic set of packagingrestrictions and evaluate different network organizations under a random traffic model. Our results indicate thatcustomizing the network topology to the packaging constraints is useful. Some of the general principles that ariseout of this study are: 1) Making the networks denser at the lower levels of the packaging hierarchy has a significantpositive impact on global communication performance, 2) It is better to organize a fixed amount of communicationbandwidth as a smaller number of high bandwidth channels, 3) Providing the processors with the ability to toleratelatencies (by using multithreading) is very useful in improving performance.

M. T. Raghunath

Abhiram  Ranade

Designing Interconnection Networks forMulti-level Packaging

We present an integrated and optimal solution to the problems of operator scheduling, module and registerallocation, and operator binding in datapath synthesis. The solution is based on an integer linear programming(ILP) model that minimizes a weighted sum of module area and total execution time under very generalassumptions of module capabilities. In particular, a module may execute an arbitrary combination of operations,possibly using different numbers of control steps for different operations. Furthermore, operations may beimplemented by a variety of modules, possibly requiring different numbers of control steps depending on themodules chosen. This generality in the complexity and mixture of modules is unqiue to our system and leads to anoptimum selection of modules to meet specified design constraints. Significant extensions include the ability toincorporate pipelined functional units and operator chaining in an integrated manner. Straightforward extensionto multi-block synthesis is discussed briefly but the details are omitted due to space considerations.

T. C. Wilson

N.  Mukherjee

M. K. Garg

D. K. Banerji

An ILP Solution for Optimum Scheduling, Moduleand Register Allocation, and OperationBinding in Datapath Synthesis

In this article we will be discussing the utilization of decomposition and reduction for development of algorithms. We willassume that a given problem instance can be somehow broken up into two smaller instances that can be solved separately.As a special case of decomposition we will define a reduction, i.e. such a decomposition that one of the resulting instancesis trivial. We will define several versions of decomposition and reduction in a hierarchical way. Different kinds will bedistinguished by their ability to preserve an optimal solution of the original instance. General schema of an algorithmutilizing the proposed notions will be introduced and a case-study demonstrating the adaptation of this schema for thecovering problem will be provided.

Michal  Serv&#237;t

Jan  Zamazal

Decomposition and Reduction: GeneralProblem-Solving Paradigms

It is well known that the hypercube has a rich set of good properties, and consequently it has been recognized an
ideal structure for parallel computation. Nevertheless, according to the current VLSI technology, the implementation
feasibility of the hypercube remains questionable when the size of the hypercube becomes large. Recent research
efforts have been concentrated on finding good alternatives to the hypercube. The star graph was shown having
many desirable properties of the hypercube, and in several aspects, the star graph is better than the hypercube.
However, we observe that the star graph as a network has several disadvantages, compared with the hypercube. In
this paper, we propose a class of new networks, the star-hypercube hybrid networks (or the SH networks). The SH
network is a simple combination of both the star graph and the hypercube. This class of networks contains the
star graph and the hypercube as subclasses. We show that the SH network is an efficient and versatile network for
parallel computation, since it shares properties of both the hypercube and the star graph, and remedies several
major disadvantages of the hypercube and the star graph. This class of networks provide more flexibility in choosing
the size, degree, number of vertices, degree of fault tolerance, etc. in designing massively parallel computing
structures feasible for VLSI implementations.

S. Q. Zheng

B. Cong

S. Bettayeb

Trade-Off Considerations in Designing Efficient VLSI
Feasible Interconnection Networks

Decomposition of system behavior along functional boundaries into interacting sequential components is a key step in
top-down system design. In this paper, we present sequential decomposition, a method for factoring sequential components
from a system specification based on interface specifications of the components. The resulting components can be
independently synthesized, or realized using off-the-shelf components. We introduce interface specification language (ISL),
based on finite-state machine semantics, to specify the input/output behavior of synchronous sub-systems. A component is
factored from a system by embedding an implementation of the complement of its interface into the system description. The
composition of a machine with its complement is shown to be isomorphic to the machine, and the composition of a machine
with an implementation of its component is shown to be a safe interaction. We apply sequential decomposition to a
non-trivial example, a special-purpose computer with Scheme programming language primitives as its instructions.

Kamlesh Rath

Venkatesh Choppella

Steven D. Johnson

Decomposition of Sequential Behavior Using
Interface Specification and Complementation

Least Common Ancestor Networks (LCANs) are introduced and shown to be a class of networks that include fattrees,baseline networks, SW-banyans and the router networks of the TRAC 1.1 and 2.0 and the CM-5. SomeLCAN properties are stated and the circuit-switched permutation routing capabilities of an important subclass areanalyzed. Simulation results for three permutation classes verify the accuracy of an iterative analysis for a randomizedrouting strategy. These results indicate that the routing strategy provides highly predictable router performancefor all permutations. An off-line routing algorithm is also given, and it is shown how to realize certain classes ofpermutations by adapting Nassimi and Sahni&#39;s, and Raghavendra and Boppana&#39;s self-routing algorithms for Benesnetworks.

Isaac D. Scherson

Chi-Kai  Chien

Least Common Ancestor Networks

This paper presents a methodology and a tool box for system-level partitioning in the behavioral domain. The methodologyis based on an extended finite state machine model. Partitioning is achieved interactively through the application of fivesystem-level transformation primitives: MOVE, MERGE, SPLIT, CUT and MAP. This scheme allows an interactiveexploration of the solution space. The result of the partitioning is a set of interconnected and heterogeneous sub-systems.The partitioning tool box which has been developed is named PARTIE PARTIF includes an evaluation feedback loop thathelps the designer estimate the quality of the design.

Tarek Ben Ismail

Kevin   O&#39;Brien

Ahmed  Jerraya

PARTIF: Interactive System-level Partitioning

A new hypercube-like topology, called the hyper Petersen (HP) network, is proposed and analyzed, which isconstructed from the well-known cartesian product of the binary hypercube and the Petersen graph of ten nodes.This topology is an attractive candidate for multiprocessor interconnection having such desirable properties asregularity, high symmetry and connectivity, and logarithmic diameter. For example, an n-dimensional hyper Petersennetwork, <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>, with N&#61;1.25 * <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msup><mml:mn>2</mml:mn><mml:mi>n</mml:mi></mml:msup></mml:mrow></mml:math> nodes is a regular graph of degree and node-connectivity n and diameter n&#8211;1, whereas an (n&#8211;1)-dimensional binary hypercube, <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>Q</mml:mi><mml:mrow><mml:mi>n</mml:mi><mml:mo>&#x2212;</mml:mo><mml:mn>1</mml:mn></mml:mrow></mml:msub></mml:mrow></mml:math>, with the same diameter covers only <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msup><mml:mn>2</mml:mn><mml:mrow><mml:mi>n</mml:mi><mml:mo>&#x2212;</mml:mo><mml:mn>1</mml:mn></mml:mrow></mml:msup></mml:mrow></mml:math> nodes, eachof degree (n&#8211;1). Thus the HP topology accommodates 2.5 times extra nodes than <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>Q</mml:mi><mml:mrow><mml:mi>n</mml:mi><mml:mo>&#x2212;</mml:mo><mml:mn>1</mml:mn></mml:mrow></mml:msub></mml:mrow></mml:math> at the cost of increasingthe node-degree by one. With the same degree and connectivity of n, the diameter of the <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math> network is one lessthan that of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>Q</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>, yet having 1.25 times larger number of nodes.Efficient routing and broadcasting schemes are presented, and node-disjoint paths in <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>, are computed evenunder faulty conditions. The versatility of the hyper Petersen networks is emphasized by embedding rings, meshes,hypercubes and several tree-related topologies into it. Contrary to the hypercubes, rings of odd lengths, and acomplete binary tree of height n&#8211;1 permit subgraph embeddings in <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>.

Sajal K. Das

Sabine  &#214;hring

Amit K. Banerjee

Embeddings into Hyper Petersen Networks: YetAnother Hypercube-Like Interconnection Topology

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VLSI Design