Reconfigurable CPLAG and Modified PFAL Adiabatic  Logic Circuits

<div>Four-phase power clock <svg height="12.4067pt" id="M11" style="vertical-align:-3.408751pt" version="1.1" viewbox="-0.0498162 -8.99795 18.7075 12.4067" width="18.7075pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><path d="M600 480C600 590 528 650 384 650H143L137 622C222 614 225 607 210 531L130 127C113 41 106 36 23 28L17 0H294L300 28C204 36 195 42 212 127L243 284L314 263C327 263 339 263 352 264C465 271 600 337 600 480ZM508 481C508 351 402 304 329 304C289 304 265 311 250 317L295 559C302 594 310 606 323 611C335 616 350 619 367 619C455 619 508 573 508 481Z" id="g113-81"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="617" vert-adv-y="617"></glyph.data></g><g transform="matrix(.0095,0,0,-0.0095,6.937,3.264)"><path d="M390 111C344 68 312 56 269 56C212 56 118 102 118 241C118 346 175 401 241 401C277 401 312 388 342 360C350 352 355 349 361 349C372 349 394 371 394 392C394 403 391 411 378 422C362 436 329 449 288 449H287C250 449 190 432 138 392C71 341 37 274 37 197C37 90 112 -12 238 -12C297 -12 363 32 407 90L390 111Z" id="g190-100"></path><glyph.data ascent="989" descent="-360" horiz-adv-x="423" vert-adv-y="423"></glyph.data></g><g transform="matrix(.0095,0,0,-0.0095,10.891,3.264)"><path d="M238 0V26C174 32 166 38 166 104V712C132 700 70 683 18 677V653C81 647 87 645 87 577V104C87 38 78 32 15 26V0H238Z" id="g190-109"></path><glyph.data ascent="989" descent="-360" horiz-adv-x="253" vert-adv-y="253"></glyph.data></g><g transform="matrix(.0095,0,0,-0.0095,13.338,3.264)"><path d="M513 0V26C475 28 448 43 413 81C379 116 277 234 258 264C301 314 319 334 344 359C383 396 404 407 473 418V443L269 434V408C317 403 320 395 299 364C280 337 250 298 228 276C213 260 195 247 165 241V712C126 699 69 682 21 677V653C82 648 87 642 87 576V104C87 40 81 32 14 26V0H237V26C173 32 165 38 165 104V215C171 217 176 218 181 218C189 218 198 212 212 196C267 129 330 49 376 -2L513 0Z" id="g190-108"></path><glyph.data ascent="989" descent="-360" horiz-adv-x="496" vert-adv-y="496"></glyph.data></g></svg>.</div>

Advances in Electronics

Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits

Figure 1