Reconfigurable CPLAG and Modified PFAL Adiabatic  Logic Circuits

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descent="-360" horiz-adv-x="468" vert-adv-y="468"></glyph.data></g></svg> variation for DFF @ RCPLAG Nand with respect to supplied voltage level.</div>

Advances in Electronics

Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits

Figure 12