Research Article
Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits
Table 1
Simulation parameters.
| | Simulation parameters | | Technology | Value | Simulation | Value |
| | Channel length | 0.180 m | Power clock | Pulse type with Trise and Tfall |
| | Min. width | 0.180 m | Input signal | Bit type |
| | Max. width | 36 microns | Delay calculation | 50% points |
| | Vton | 0.3932664 | Data sequence | 8 cycles |
| | TOX | 4.10E − 09 | Power clock time period | 40 s |
| | MOS Gate Capacitance Model: |
| | capmod = 0 |
| | Conditions: |
| | Voltage | 1 V to 5 V (+0.5 V) |
| | Temperature | 25, 30, 40, 70, 100, 200 |
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