Reconfigurable CPLAG and Modified PFAL Adiabatic  Logic Circuits

<table class="table-group" id="tab2"><tr><td><table class="table"><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr><td align="left">AND CKT. IMP.</td><td align="center">Pavg_Vpuls (W)</td></tr><tr><td align="center" colspan="2"><hr/></td></tr><tr><td align="left">PFAL</td><td align="center">13.58 <i>μ</i></td></tr><tr><td align="center" colspan="2"><hr/></td></tr><tr><td align="left">ECRL</td><td align="center">6.91 <i>µ</i></td></tr><tr><td align="center" colspan="2"><hr/></td></tr><tr><td align="left">RCPLAG</td><td align="center">12 n</td></tr><tr class="table-tr"><td colspan="2"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Advances in Electronics

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Table 2

Table 2: Reconfigurable CPLAG and Modified PFAL Adiabatic  Logic Circuits 