Reconfigurable CPLAG and Modified PFAL Adiabatic  Logic Circuits

<table class="table-group" id="tab5"><tr><td><table class="table"><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr><td align="left">ADDER CKT. IMP.</td><td align="center">Pavg_Vpuls (W)</td></tr><tr><td align="center" colspan="2"><hr/></td></tr><tr><td align="left">CPL</td><td align="center">6.11<i>E</i> − 04</td></tr><tr><td align="center" colspan="2"><hr/></td></tr><tr><td align="left">CPL_PCLK</td><td align="center">2.22<i>E</i> − 04</td></tr><tr><td align="center" colspan="2"><hr/></td></tr><tr><td align="left">CPLAG PCLK</td><td align="center">5.87<i>E</i> − 05</td></tr><tr><td align="center" colspan="2"><hr/></td></tr><tr><td align="left">CPLAG VDD</td><td align="center">6.18<i>E</i> − 05</td></tr><tr class="table-tr"><td colspan="2"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Advances in Electronics

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Table 5

Table 5: Reconfigurable CPLAG and Modified PFAL Adiabatic  Logic Circuits 