FPGA Interconnect Topologies Exploration

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="259837.fig.005a" src="https://static.hindawi.com/articles/ijrc/volume-2009/259837/figures/259837.fig.005a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Partitioned netlist</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="259837.fig.005b" src="https://static.hindawi.com/articles/ijrc/volume-2009/259837/figures/259837.fig.005b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Routed netlist with conflict</td></tr></table></td></tr><tr class="fig-image" id="c"><td><img alt="259837.fig.005c" src="https://static.hindawi.com/articles/ijrc/volume-2009/259837/figures/259837.fig.005c.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(c) </b>Routed netlist with no conflict</td></tr></table></td></tr></table>

<table>A netlist routing example showing architecture Rent's parameter increase.</table>

International Journal of Reconfigurable Computing

FPGA Interconnect Topologies Exploration

Figure 5