A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="163542.fig.007a" src="https://static.hindawi.com/articles/ijrc/volume-2012/163542/figures/163542.fig.007a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Inter-PE link usage for each execution cycle with nontransient copy enabled and disabled</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="163542.fig.007b" src="https://static.hindawi.com/articles/ijrc/volume-2012/163542/figures/163542.fig.007b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Bypassing register usage for each execution cycle with nontransient copy usage breakdown</td></tr></table></td></tr></table>

<table>Performance impact of nontransient copies.</table>

International Journal of Reconfigurable Computing

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Figure 7

Figure 7: A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance 