FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Figure 9

High-level decoder architecture showing the -fold parallelization of the NPUs with an emphasis on the splitting of the sign and the minimum computation given in (5). Note that, other computations in (3)–(6) are not shown for simplicity here. For both the pipelined and the nonpipelined versions, processing schedule for the inner block processing loop is as per Figure 6 and that for the outer layer processing loop is as per Figure 7.