Research Article
FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis
Table 4
Block index matrix
showing the valid blocks (bold) to be processed.
| Layers | Blocks | | | | | | | | |
| | 0 | 4 | 6 | 8 | 10 | 12 | 13 | −1 | | 0 | 2 | 4 | 8 | 9 | 13 | 14 | −1 | | 0 | 4 | 5 | 8 | 9 | 14 | 15 | −1 | | 0 | 1 | 4 | 7 | 8 | 15 | 16 | −1 | | 0 | 3 | 4 | 7 | 8 | 16 | 17 | −1 | | 0 | 4 | 6 | 8 | 11 | 17 | 18 | −1 | | 0 | 1 | 2 | 6 | 8 | 12 | 18 | 19 | | 0 | 4 | 5 | 8 | 10 | 19 | 20 | −1 | | 0 | 4 | 5 | 8 | 11 | 20 | 21 | −1 | | 1 | 3 | 4 | 8 | 9 | 21 | 22 | −1 | | 0 | 1 | 3 | 4 | 10 | 22 | 23 | −1 | | 0 | 2 | 4 | 7 | 8 | 11 | 12 | 23 |
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