FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Table 6

Rearranged block index matrix used for our work, showing the valid blocks (bold) to be processed.

Layers	Blocks
		0	4	8	13	6	10	12	−1
	9	0	4	8	13	14	2	−1
	15	9	0	4	8	5	14	−1
	7	15	16	0	4	8	1	−1
	17	7	3	16	0	4	8	−1
	6	17	18	11	−1	0	4	8
	19	6	0	8	1	2	18	12
	4	19	5	0	8	20	10	−1
	21	4	11	5	0	8	20	−1
	1	21	4	3	22	9	8	−1
	0	1	23	4	3	22	10	−1
	8	0	2	23	4	12	7	11