Research Article

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Table 7

LDPC decoder IP FPGA resource utilization and throughput after mapping onto the Xilinx Kintex-7 FPGA.

ā€‰

DeviceKintex-7k410tKintex-7k410t
Throughput (Mb/s)337608
FF (%)9.15.3
BRAM (%)4.76.4
DSP48 (%)5.25.2
LUT (%)8.78.2