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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
/
2017
/
Article
/
Tab 7
/
Research Article
FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis
Table 7
LDPC decoder IP FPGA resource utilization and throughput after mapping onto the Xilinx
Kintex-7 FPGA
.
ā
Device
Kintex-7k410t
Kintex-7k410t
Throughput (Mb/s)
337
608
FF (%)
9.1
5.3
BRAM (%)
4.7
6.4
DSP48 (%)
5.2
5.2
LUT (%)
8.7
8.2