FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Table 9

Performance and resource utilization, after mapping onto the FPGA, for the HARQ system (that supports both Type-I and Type-II mode of operation) on the NI USRP-2953R containing the Xilinx Kintex-7 (410t) FPGA.

	Utilization
Clock rate (MHz)	80
Time to generate VHDL (min)	5
Total slice (%)	54
LUT (%)	32
FF (%)	19
DSP (%)	12
BRAM (%)	30