Research Article
Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language
Table 1
IP core benchmark results for Xilinx, OpenCores, and SDR cores.
| Source | Cores | Slices (23038) | % | LUTs (92152) | % | Registers (184304) | % | RAM (21680) | % | DSP48A1s (180) | % | BUFGs (16) | % | Maximum Clock Frequency (MHz) |
| Xilinx library | FIR | 30 | 1 | 50 | 1 | 96 | 1 | 13 | 1 | 1 | 1 | 1 | 1 | 303 | FFT | 885 | 3 | 2294 | 2 | 3403 | 1 | 607 | 2 | 16 | 8 | 1 | 1 | 141 | DDC | 680 | 2 | 1223 | 1 | 2179 | 1 | 472 | 2 | 7 | 3 | 1 | 1 | 134 |
| OpenCores | FIR | 1556 | 6 | 3872 | 4 | 691 | 1 | 0 | 0 | 21 | 11 | 1 | 1 | 80 | IIR | 247 | 1 | 857 | 1 | 864 | 1 | 0 | 0 | 72 | 40 | 1 | 1 | 66 | FFT | 1209 | 5 | 2768 | 3 | 3120 | 1 | 1024 | 4 | 16 | 8 | 1 | 1 | 84 |
| SDR cores | FIR | 43 | 1 | 132 | 1 | 304 | 1 | 0 | 0 | 30 | 16 | 1 | 1 | 130 | IIR | 144 | 1 | 376 | 1 | 492 | 1 | 0 | 0 | 36 | 20 | 1 | 1 | 94 | FFT | 930 | 4 | 2518 | 2 | 1267 | 1 | 642 | 2 | 16 | 8 | 1 | 1 | 118 | DDC | 1404 | 6 | 4024 | 4 | 5179 | 2 | 0 | 0 | 2 | 1 | 1 | 1 | 129 |
| ā | Gbe | 1205 | 5 | 2701 | 1 | 2928 | 1 | 411 | 1 | 0 | 0 | 7 | 43 | 165 | FMC150 | 631 | 2 | 1335 | 1 | 1272 | 1 | 142 | 1 | 0 | 0 | 8 | 50 | 184 | FM Rec. | 1404 | 6 | 4024 | 4 | 5179 | 2 | 0 | 0 | 2 | 1 | 1 | 6 | 154 |
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