Research Article
Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal
Figure 6
Image showing tile-hopping. (a) Image-level view showing tiles. (b) DRAM-level view showing tile placement while writing. (c) DRAM-level view showing column reading from the tiles.
(a) Dataset view |
(b) Memory view |
(c) Memory view |