2-Layered Architecture of Vague Logic Based Multilevel Queue Scheduler

Table 1

Sample task set.

I/O bound tasks				CPU bound tasks
Task	Arrival time	Priority	Burst time	Task	Arrival time	Priority	Burst time
T1	0	9	8	C1	0	3	20
T2	0	8	9	C2	0	2	25
T3	0	7	5	C3	30	3	30
T4	21	6	6	C4	35	2	35
T5	25	5	7	C5	40	3	15
T6	38	7	4
T7	40	8	3
T8	45	6	5
T9	55	6	6
T10	57	8	5
T11	60	5	4