From Coherent States in Adjacent Graphene Layers toward Low-Power Logic Circuits
Figure 1
(a) Schematic illustration of BiSFET (with dielectrics not shown for clarity). (b) Qualitative estimation of interlayer current versus interlayer voltage for balanced and unbalanced charged distributions, consistent with the BiSFET model used in Section 2 as required for specificity. Arrows in (b) illustrate inverter operation as discussed in Section 3.
